In a lateral MOSFET, the source and drain diffusions are located on a single surface of a semiconductor substrate. While lateral MOSFETs can be constructed of long alternating stripes of source and drain regions separated by a gate stripe, it is well known that a closed cell arrangement typically provides a lower on-resistance in a given area. In such closed cell lateral MOSFET designs the cells are arranged in rows and columns as shown in FIG. 1, wherein cells alternate between source and drain regions in both columns and rows. Source and drain metal interconnection lines are then deposited diagonally, such that the source and drain metal lines alternate with one another across the face of the chip.
FIGS. 2A and 2B illustrate top and cross-sectional views, respectively, of a typical cell. In this example, a diffusion 20 of N+ type material is made in a P substrate 21. The N+ diffusion is accessed by a metal contact 22. The metal contact 22 is surrounded laterally by a layer of gate material 23, typically polysilicon, which is separated from the top surface of substrate 21 by a gate oxide layer 24. A thermal oxide layer 25 and a thick oxide layer 26 separate the polysilicon gate 23 from the metal contact 22.
To prevent a short between metal contact 22 and polysilicon gate 23, which would destroy the MOSFET, a minimal clearance, shown as "x" in FIGS. 2A and 2B, must maintained between them. If this minimal distance is not maintained, errors in alignment, for example, may create a short between the metal contact and the gate. A typical value of x is 1 .mu.m. To minimize the on-resistance of the transistor, it is desirable to have the cross-sectional area of the metal contact 22 be as large as possible for a given size opening in the gate. Therefore, assuming that the opening in the polysilicon gate is a square, the cross-section of metal contact 22 would ordinarily be a smaller square separated from the gate by the minimal distance x on all sides.
FIG. 3 is a top plan view of a junction between the metal contact 22 and one of the diagonal metal lines, designated by the reference numeral 30, which illustrates the problem that occurs at this location. Metal contact 22 should be spaced at least a minimal distance from the edge of metal line 30, a distance which is designated as "v" in FIG. 3. Otherwise, a slight misalignment of the metal line may expose the contact. If the metal line does not cover the contact, then subsequent processing may etch holes through the silicon, destroying the junction and shorting out the device. It is well known that no portion of contact 22 should be left uncovered by metal line 30. As is evident from FIG. 3, metal 30 would have to be widened (see dashed lines 30A) to maintain the required separation between metal contact 22 and the edges of the meal line. This would very likely require that the source and drain cells be spaced further apart than is desirable fore minimizing the on-resistance of the MOSFET.
Alternatively, the minimal distance v could be maintained by rotating metal contact 22 through a 45.degree. angle (as shown by the dashed lines). However, this will result in metal contact 22 being closer than the minimal distance x to the polysilicon gate 23. (The opening in gate 23 is illustrated by the dotted and dashed line in FIG. 3.)
In the metal contact structure of this invention, the cross-sectional area of the metal contact is maximized, while the minimal clearance between both the edge of the gate and the edge of a diagonal metal line is maintained.